Condition: Used

Used Agilent 16550A 102-channel state/timing analysis module for the HP/Agilent 16500 logic analysis system. The board is labelled '100 MHz STATE / 500 MHz TIMING' and carries serial number US34515555. Five Hewlett-Packard probe pod ribbon cables are included.

Included in the sale:
• Agilent 16550A 102-Channel State/Timing Module (serial no. US34515555)
• Ribbon cable with Pod 1 connector (brown label)
• Ribbon cable with Pod 2 connector (red label)
• Ribbon cable with Pod 3 connector (tan/beige label)
• Ribbon cable with Pod 4 connector (yellow label)
• Ribbon cable with Pod 5 connector (teal/green label)

The images provided are of the actual item you will receive. Please review them carefully for the cosmetic condition and what is included in the sale.

The Agilent (HP/Keysight) 16550A is a 102-channel state and timing analysis module for use in the HP/Agilent 16500 modular logic analysis system mainframe. It delivers industry-standard state and timing analysis performance for high-speed digital design debug and verification. All channels can perform either state or timing functions, and the module can be set up to perform simultaneous, fully time-correlated state analysis on some channels and timing analysis on others — without the need to move or change probes.

Two 16550A cards can be interconnected to expand channel count to 204. A half-channel acquisition mode is also available, which reduces the channel width by half but doubles memory depth from 4K to 8K samples per channel. Transitional timing mode captures events that are seconds apart while maintaining up to 4 ns resolution, by storing data only when a transition occurs — effectively extending total capture time without sacrificing resolution.

Key Specifications:
Number of Channels: 102 (single card); expandable to 204 with a second card
Data Channels: 96 data + 6 clock channels (single card)
State Analysis Speed: 100 MHz maximum
Timing Analysis Speed: 500 MHz maximum
Timing Resolution: 2 ns (full channel); 4 ns (transitional timing)
Acquisition Memory Depth (State Mode): 4K samples per channel
Acquisition Memory Depth (Timing Mode): 8K samples per channel (half-channel mode)
Setup/Hold Window: 3.5 ns variable
Threshold Levels: TTL, ECL, or user-defined (-6.0 V to +6.0 V)
Probe Pods: 6 pods (each 16 data channels + 1 clock)
Compatible Mainframes: HP/Agilent 16500A, 16500B, 16500C, 16700A, 16700B series
Form Factor: Single-slot plug-in module
Bus Interfaces Supported: HP-IB, RS-232-C, SCSI, VME, VXI, ISA, EISA, MCA, PCI, JTAG, SBus, PCMCIA, FDDI, Futurebus+
Use Cases: High-speed digital design debug and verification, firmware development, state machine tracing, timing diagram capture, protocol analysis, bus interface debugging

HP 16550A 100-MHz State/500-MHz Timing Logic Analyzer User's Reference Manual (Apr 1994): Download PDF

Agilent 16550A Logic Analyzer Help Guide — measurement setup and operation reference: Download PDF

Agilent/HP 16550A Programmer's Guide — remote programming and command reference: Download PDF

Agilent/HP 16550A Product Datasheet — features, specifications and ordering information: Download PDF